![]() Line 33: what is sel it's not defined in your tmux module. Also learn to indent code, haven't you ever written C and been told to indent stuff? Use whitespace in your code from now on it's free (or nearly so) and it makes code much easier to read, instead of a packed messes of characters you have to really look at to determine if something starts or ends. Lines 29-33: #10a, etc might not even compile correctly as there is no white space separating the number from the signal name. ![]() s is the bus name and using your silly names s0 and s1 in the testbench the connection should be. Line 25: s0 and s1 are NOT the way you define the ports for a bus. ![]() Line 12: sel is not declared and is probably supposed to be s ![]() Lines 10, 12: elseif is not a proper verilog keyword it is: else if Lines 1-4: sucky antiquated usage of pre-Verilog 2001 module port declaration syntax.Use Verilog 2001 syntax it's much cleaner and requires no repeating of the post names in two places. Re: Verilog Hardware description language ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |